This invention relates to switched capacitor circuits or networks and more particularly to switched capacitor circuit replacements for resistors.
There is currently much interest in the simulation of electrical components such as resistors and inductors using switched capacitor circuits so that filter networks can be implemented in fully integrated circuit form. Floating and/or grounded switched capacitor resistors are generally described in the references Sampled Analog Filtering Using Switched Capacitors as Resistor Equivalents by J. T. Caves et al, IEEE Journal of Solid State Circuits, Vol. 12, No. 6, pp 592-599, December 1977; MOS Sampled Data Recursive Filters Using Switched Capacitor Integrators by B. J. Hosticka et al, IEEE Journal of Solid State Circuits, Vol. 12, No. 6, pp 600-608, December 1977; Switched Capacitor Filter Design Using the Bilinear z-Transform by G. C. Temes et al, IEEE Transactions on Circuits and Systems, Vol. 25, No. 12, pp 1039-1044, December 1978; and Derivation of Switched Capacitor Filters from Active-RC Prototypes by G. C. Temes, Electronics Letters, Vol. 14, No. 12, pp 361-362, June, 1978. A number of the previously existing switched capacitor resistors are susceptible to top and/or bottom plate parasitic capacitance effects.
An object of this invention is the provision of novel switched capacitor circuits for simulating bilinear resistors.
Another object is the provision of a switched capacitor bilinear resistor simulation circuit that may be connected so as to be relatively insensitive to both top and bottom plate parasitic capacitance effects associated with an integrated capacitor thereof.